Senior IP Design Engineer - India
Aeva, Inc., India
Experience
1 Year
Salary
0 - 0
Job Type
Job Shift
Job Category
Traveling
No
Career Level
Telecommute
No
Qualification
As mentioned in job details
Total Vacancies
1 Job
Posted on
Feb 27, 2024
Last Date
Mar 16, 2024
Location(s)
Job Description
Role Summary:As a key player on the Design team, you will participate in the RTL design and development of the signal processing path for Aeva’s 4-D Lidar processing chip. You will be responsible for implementing and/or integrating sub-components of the design in ASIC.What you'll be doing:
- Develop sub-components of the digital signaling pipeline.
- Code RTL, Test, and Validate Aeva-specific sub-components.
- Implement additional SOC functionality including functional safety and robustness functions.
- Focus on developing efficient, highly reliable, highly available, robust functionality.
- Work with Architects, design engineers, verification engineers, and System software teams to ensure that the SOC meets its functional, performance, and power targets.
- 8+ years of experience in the design and verification of advanced ARM or similar processor Architecture based SOCs
- Experience and knowledge of DSP designs, algorithms, and signal processing functionality. Ability to achieve high performance and low power targets.
- Experience writing Verilog RTL Code.
- Working experience and knowledge in AMBA protocols, LPDDR, Ethernet, MIPI, and high-speed Serdes etc.
- Proficient in debugging complex SOC or CPU core designs
- Desire to learn amp; implement groundbreaking new processes and methodology for continuous improvement
- Experience in FPGA designs, pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
- Post-silicon bring-up and validation planning and execution
- Diagnostics Firmware development and validation
Job Specification
Job Rewards and Benefits
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